Generally, a master slice or gate array semiconductor device is arranged such that basic elements such as transistors and the like are arranged in a regular pattern on a master chip of a certain size, so that the customizing can be carried out by adding the wiring process.
A conventional gate array master chip 2 as shown in FIG. 2 which generally includes an internal logic circuit formation region 3 comprising a central cell array region 5 and a peripheral input/output cell region 6; and a bonding pad formation region 4 containing a plurality of bonding pads 7 around the input/output cell region 6, wherein the size of the master chip 2 has been normalized to a fixed level.
However, the size or area of the master chip is determined by the number of gates contained therein, and therefore a supplier of semiconductor devices manufactures and prepares different master wafers according to the number of gates in conformity with customer demand.
In turn, semiconductor devices are fabricated through the wiring process in gate arrays of a size the same as or larger than those required for the specific customized products.
Thus, conventional gate arrays are standardized, and therefore, designing to optimum chip size is too difficult for meeting customer demand. Additionally, a further disadvantage is that the production and the product control must be implemented for each size separately. Further, because only the limited gates provided in the standardized chip can be used, freedom of circuitry design is reduced.